1. Field of the Invention
The present invention relates to a wafer level package for heat dissipation and a method of manufacturing the same.
2. Description of the Related Art
A wafer level chip scale package (WLCSP), which is a package prepared before being cut into individual dies, is manufactured in such a way that a wafer is simultaneously subjected to collective processes of forming redistribution layers and solder balls at a wafer level and the wafer including the solder balls thereon is cut into chips. In the manufacture of the wafer level chip scale package, redistribution or rerouting of pads of the dies is employed.
Recently, in electronic component industries, the number of I/Os of a chip is continuously increased and wafer packages are increasingly becoming multifunctional and complicated. In accordance with this trend, research into improving heat dissipation performance of a wafer level chip scale package is being intensively conducted.
FIGS. 1 to 6 show a conventional process of manufacturing a wafer level package including a heat dissipation plate in the process sequence. Hereinafter, the process of manufacturing a wafer level package will be briefly described.
As shown in FIG. 1, a heat dissipation plate 12 for improving heat dissipation performance is first prepared.
As shown in FIG. 2, a cavity 14 which is adapted to allow a die to be inserted therein is formed in the heat dissipation plate 12.
As shown in FIG. 3, a die 16 which includes pads 18 disposed on a side thereof is aligned so as to be mounted in the cavity 14.
As shown in FIG. 4, the die 16 is mounted in the cavity using an adhesive 20. More specifically, the die 16 is mounted in the cavity 14 using an adhesive 20 disposed between a lateral wall of the die 16 and an inner wall of the cavity 14.
As shown in FIG. 5, a buildup layer 22 having a circuit layer 26 and an insulating layer 24 is disposed on the heat dissipation plate 12 and the die 16 such that the circuit layer 26 is connected to the pads 18.
As shown in FIG. 6, a solder resist layer 28 having openings is disposed on the outermost surface of the buildup layer 22 such that land parts of the circuit layer 26 are exposed through the openings of the solder resist layer 28, and solder balls 30 are attached to the land parts, thus providing a wafer level package 10.
However, the conventional wafer level package 10 has trouble in that the back side of the die is exposed to the outside and is thus damaged by the external environments, and it is hard to make the heat dissipation plate 12 flush with the die at a desired height. In particular, although the side of the die 16 on which the pads 18 are disposed is shown in FIG. 4 as being flush with the heat dissipation plate 12, there may be a height difference between the die 16 and the heat dissipation plate 12 in an actual manufacturing process. When a height difference is present between the die 16 and the heat dissipation plate 12, an additional insulating layer 24 must be first formed on one side of the die 16 so as to allow easy formation of the circuit layer 26.